The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to connect interconnect structures with copper nanowires.
New integrated circuit technologies include three-dimensional integrated circuits. One type of 3D integrated circuit may include two or more layers of active electronic components stacked vertically and electrically joined with through-substrate vias and solder bumps. The 3D integrated circuit may provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through-silicon-vias. The 3D integrated circuit described above may be fabricated in any number of known methods. Some 3D integrated circuits may include a silicon interposer which may be used to re-direct circuitry between a ship carrier and one or more top chips.
Copper pillars are a chip-to-chip interconnect technology used to enhance electromigration performance, to reduce the pitch of interconnects, and to provide for a larger gap, or standoff, between individual chips for underfill flow over conventional solder controlled collapse chip connections (C4 connections). In copper pillar technology, a small amount of solder is still required to connect and join the copper pillars of one chip to a pad of another chip or substrate.